? 1999 fairchild semiconductor corporation ds010234 www.fairchildsemi.com july 1989 revised november 1999 74acq240 ? 74actq240 quiet series ? octal buffer/line driver with 3-state outputs 74acq240 74actq240 quiet series ? octal buffer/line driver with 3-state outputs general description the acq/actq240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved pc board density. the acq/ actq utilizes fairchild?s quiet series ? technology to guarantee quiet output switching and improve dynamic threshold performance. fact quiet series ? features gto ? output control and undershoot corrector in addition to a split ground bus for superior performance. features i cc and i oz reduced by 50% guaranteed simultaneous switching noise level and dynamic threshold performance guaranteed pin-to-pin skew ac performance improved latch-up immunity inverting 3-state outputs drive bus lines or buffer memory address registers outputs source/sink 24 ma faster prop delays than the standard act240 ordering code: device also available in tape and reel. specify by appending suffix letter ? x ? to the ordering code. connection diagram pin descriptions fact ? , quiet series ? , fact quiet series ? , and gto ? are trademarks of fairchild semiconductor corporation. order number package number package description 74acq240sc m20b 20-lead small outline integrated circuit (soic)jedec ms-013, 0.300 ? wide body 74acq240sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74acq240pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 ? wide 74actq240sc m20b 20-lead small outline integrated circuit (soic)jedec ms-013, 0.300 ? wide body 74actq240sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74actq240qsc mqa20 20-lead quarter size outline package (qsop), jedec mo-137, 0.150 ? wide pin names description oe 1 , oe 2 3-state output enable inputs i 0 ? i 7 inputs o 0 ? o 7 outputs
www.fairchildsemi.com 2 74acq240 74actq240 logic symbol ieee/iec truth tables h = high voltage level l = low voltage level x = immaterial z = high impedance inputs outputs oe 1 i n (pins 12, 14, 16, 18) ll h lh l hx z inputs outputs oe 2 i n (pins 3, 5, 7, 9) l l h lh l hx z
3 www.fairchildsemi.com 74acq240 74actq240 absolute maximum ratings (note 1) recommended operating conditions note 1: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact ? circuits outside databook specifications. dc electrical characteristics for acq supply voltage (v cc ) ? 0.5v to + 7.0v dc input diode current (i ik ) v i = ? 0.5v ? 20 ma v i = v cc + 0.5v + 20 ma dc input voltage (v i ) ? 0.5v to v cc + 0.5v dc output diode current (i ok ) v o = ? 0.5v ? 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) ? 0.5v to v cc + 0.5v dc output source or sink current (i o ) 50 ma dc v cc or ground current per output pin (i cc or i gnd ) 50 ma storage temperature (t stg ) ? 65 c to + 150 c dc latch-up source or sink current 300 ma junction temperature (t j ) pdip 140 c supply voltage (v cc ) acq 2.0v to 6.0v actq 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ? v/ ? t acq devices v in from 30% to 70% of v cc v cc @ 3.0v, 4.5v, 5.5v 125 mv/ns minimum input edge rate ? v/ ? t actq devices v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v 125 mv/ns symbol parameter v cc t a = + 25 c t a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1v input voltage 4.5 2.25 3.15 3.15 v or v cc ? 0.1v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1v input voltage 4.5 2.25 1.35 1.35 v or v cc ? 0.1v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 output voltage 4.5 4.49 4.4 4.4 v i out = ? 50 a 5.55.495.4 5.4 v in = v il or v ih 3.0 2.56 2.46 i oh = ? 12 ma 4.5 3.86 3.76 v i oh = ? 24 ma 5.5 4.86 4.76 i oh = ? 24 ma (note 2) v ol maximum low level 3.0 0.002 0.1 0.1 output voltage 4.5 0.001 0.1 0.1 v i out = 50 a 5.5 0.001 0.1 0.1 v in = v il or v ih 3.0 0.36 0.44 i ol = 12 ma 4.5 0.36 0.44 v i ol = 24 ma 5.5 0.36 0.44 i ol = 24 ma (note 2) i in maximum input 5.5 0.1 1.0 av i = v cc , gnd (note 4) leakage current i old minimum dynamic 5.5 75 ma v old = 1.65v max i ohd output current (note 3) 5.5 ? 75 ma v ohd = 3.85v min i cc maximum quiescent 5.5 4.0 40.0 av in = v cc or gnd (note 4) supply current i oz maximum 3-state 5.5 0.25 2.5 a v i (oe) = v il , v ih leakage current v i = v cc , gnd v o = v cc , gnd
www.fairchildsemi.com 4 74acq240 74actq240 dc electrical characteristics for acq (continued) note 2: all outputs loaded; thresholds on input associated with output under test. note 3: maximum test duration 2.0 ms, one output loaded at a time. note 4: i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . note 5: plastic dip package. note 6: max number of outputs defined as (n). data inputs are driven 0v to 5v. one output @ gnd. note 7: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to 5v (acq). input-under-test switching: 5v to threshold (v ild ), 0v to threshold (v ihd ), f = 1 mhz. dc electrical characteristics for actq note 8: all outputs loaded; thresholds on input associated with output under test. note 9: maximum test duration 2.0 ms, one output loaded at a time. note 10: plastic dip package. note 11: max number of data inputs defined as (n). n ? 1 data inputs are driven 0v to 3v. one data input @ v in = gnd. note 12: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to 3v (actq). input-under-test switching: 3v to threshold (v ild ), 0v to threshold (v ihd ), f = 1 mhz. symbol parameter v cc t a = + 25 c t a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v olp quiet output 5.0 1.1 1.5 v figure 1, figure 2 maximum dynamic v ol (note 5)(note 6) v olv quiet output 5.0 ? 0.6 ? 1.2 v figure 1, figure 2 minimum dynamic v ol (note 5)(note 6) v ihd minimum high level dynamic input voltage 5.0 3.1 3.5 v (note 5)(note 7) v ild maximum low level dynamic input voltage 5.0 1.9 1.5 v (note 5)(note 7) symbol parameter v cc t a = + 25 c t a = ? 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc ? 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc ? 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 vi out = ? 50 a output voltage 5.5 5.49 5.4 5.4 v in = v il or v ih 4.5 3.86 3.76 v i oh = ? 24 ma 5.5 4.86 4.76 i oh = ? 24 ma (note 8) v ol maximum low level 4.5 0.001 0.1 0.1 vi out = 50 a output voltage 5.5 0.001 0.1 0.1 v in = v il or v ih 4.5 0.36 0.44 v i ol = 24 ma 5.5 0.36 0.44 i ol = 24 ma (note 8) i in maximum input leakage current 5.5 0.1 1.0 av i = v cc , gnd i oz maximum 3-state 5.5 0.25 2.5 a v i = v il , v ih leakage current v o = v cc , gnd i cct maximum i cc /input 5.5 0.6 1.5 ma v i = v cc ? 2.1v i old minimum dynamic 5.5 75 ma v old = 1.65v max i ohd output current (note 9) 5.5 ? 75 ma v ohd = 3.85v min i cc maximum quiescent supply current 5.5 4.0 40.0 av in = v cc or gnd v olp quiet output maximum 5.0 1.1 1.5 v figure 1, figure 2 dynamic v ol (note 10)(note 11) v olv quiet output minimum 5.0 ? 0.6 ? 1.2 v figure 1, figure 2 dynamic v ol (note 10)(note 11) v ihd minimum high level dynamic input voltage 5.0 1.9 2.2 v (note 10)(note 12) v ild maximum low level dynamic input voltage 5.0 1.2 0.8 v (note 10)(note 12)
5 www.fairchildsemi.com 74acq240 74actq240 ac electrical characteristics for acq note 13: voltage range 5.0 is 5.0v 0.5v voltage range 3.3 is 3.3 0.3v. note 14: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. ac electrical characteristics for actq note 15: voltage range 5.0 is 5.0v 0.5v note 16: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. capacitance v cc t a = + 25 ct a = ? 40 c to + 85 c symbol parameter (v) c l = 50 pf c l = 50 pf units (note 13) min typ max min max t phl propagation delay 3.3 2.0 7.0 10.0 2.0 10.5 ns t plh data to output 5.0 1.5 5.0 6.5 1.5 7.0 t pzl output enable time 3.3 2.5 8.0 12.0 2.5 12.5 ns t pzh 5.0 1.5 5.5 8.0 1.5 8.5 t phz output disable time 3.3 1.0 8.5 13.5 1.0 14.0 ns t plz 5.0 1.0 6.0 9.0 1.0 9.5 t oshl output to output skew 3.3 1.0 1.5 1.5 ns t oslh data to output (note 14) 5.0 0.5 1.0 1.0 v cc t a = + 25 ct a = ? 40 c to + 85 c symbol parameter (v) c l = 50 pf c l = 50 pf units (note 15) min typ max min max t phl propagation delay 5.0 1.5 5.5 7.0 1.5 7.5 ns t plh data to output t pzl , t pzh output enable time 5.0 1.5 6.5 8.5 1.5 9.0 ns t phz , t plz output disable time 5.0 1.0 7.0 9.5 1.0 10.0 ns t oshl output to output skew 5.0 0.5 1.0 1.0 ns t oslh data to output (note 16) symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c pd power dissipation capacitance 70 pf v cc = 5.0v
www.fairchildsemi.com 6 74acq240 74actq240 fact noise characteristics the setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. the following is a brief description of the setup used to measure the noise characteristics of fact. equipment: hewlett packard model 8180a word generator pc-163a test fixture tektronics model 7854 oscilloscope procedure: 1. verify test fixture loading: standard load 50 pf, 500 ? . 2. deskew the hfs generator so that no two channels have greater than 150 ps skew between them. this requires that the oscilloscope be deskewed first. it is important to deskew the hfs generator channels before testing. this will ensure that the outputs switch simultaneously. 3. terminate all inputs and outputs to ensure proper load- ing of the outputs and that the input levels are at the correct voltage. 4. set the hfs generator to toggle all but one output at a frequency of 1 mhz. greater frequencies will increase dut heating and affect the results of the measure- ment. 5. set the hfs generator input levels at 0v low and 3v high for act devices and 0v low and 5v high for ac devices. verify levels with an oscilloscope. note 17: v ohv and v olp are measured with respect to ground reference. note 18: input pulses have the following characteristics: f = 1mhz, t r = 3ns, t f = 3 ns, skew < 150 ps. figure 1. quiet output noise voltage waveforms v olp /v olv and v ohp /v ohv : determine the quiet output pin that demonstrates the greatest noise levels. the worst case pin will usually be the furthest from the ground pin. monitor the output volt- ages using a 50 ? coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. measure v olp and v olv on the quiet output during the worst case transition for active and enable. measure v ohp and v ohv on the quiet output during the worst case active and enable transition. verify that the gnd reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. v ild and v ihd : monitor one of the switching outputs using a 50 ? coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. first increase the input low voltage level, v il , until the output begins to oscillate or steps out a min of 2 ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input low voltage level at which oscillation occurs is defined as v ild . next decrease the input high voltage level, v ih , until the output begins to oscillate or steps out a min of 2 ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input high voltage level at which oscillation occurs is defined as v ihd . verify that the gnd reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. figure 2. simultaneous switching test circuit
7 www.fairchildsemi.com 74acq240 74actq240 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 ? wide body package number m20b
www.fairchildsemi.com 8 74acq240 74actq240 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
9 www.fairchildsemi.com 74acq240 74actq240 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead quarter size outline package (qsop), jedec mo-137, 0.150 ? wide package number mqa20
www.fairchildsemi.com 10 74acq240 74actq240 quiet series ? octal buffer/line driver with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 ? wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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